| Name | Version | Summary | date |
| vsc-dm |
0.0.1.14003999796 |
Core Verification Stimulus and Coverage library |
2025-03-22 01:52:37 |
| zuspec-be-py |
0.0.1.14003524440 |
Co-specification of hardware, software, design, and test behavior |
2025-03-22 00:56:45 |
| vsc-solvers |
0.0.1.13937968163 |
Core Verification Stimulus and Coverage library |
2025-03-19 03:09:55 |
| pyhdl-if |
0.0.2.13849311719 |
Python interface for HDL programming interfaces |
2025-03-14 03:34:25 |
| ichier |
0.2.4 |
Integrated Circuit Hierarchy |
2025-02-23 11:23:12 |
| zuspec-cli |
0.0.1.13321310739 |
Co-specification of hardware, software, design, and test behavior |
2025-02-14 02:34:16 |
| tsfpga |
13.1.1 |
A flexible and scalable development platform for modern FPGA projects |
2025-02-12 13:43:08 |
| zuspec-sv |
0.0.9 |
Core ARL data model library |
2025-02-12 03:02:40 |
| zuspec-be-sw |
0.0.9 |
Backend library to generate software output |
2025-02-12 02:45:03 |
| zuspec-arl-eval |
0.0.9 |
Core ARL data model library |
2025-02-12 02:44:37 |
| zuspec-arl-dm |
0.0.9 |
Core ARL data model library |
2025-02-12 02:37:06 |
| ivpm |
1.1.4.13232874283 |
IVPM (IP and Verification Package Manager) is a project-internal package manager. |
2025-02-10 03:20:24 |
| uvm-python |
0.4.0 |
uvm-python UVM implementation in Python on top of cocotb |
2025-02-09 13:12:28 |
| pyslang |
8.0.0 |
Python bindings for slang, a library for compiling SystemVerilog |
2025-02-07 11:59:48 |
| hdltree |
0.3.4 |
Pure Python HDL parser, plus symbol generator and sphinx domain |
2025-02-06 01:22:43 |
| pytest-fv |
0.0.1.13065020602 |
pytest extensions to support running functional-verification jobs |
2025-01-31 02:09:45 |
| zuspec-dataclasses |
0.0.1.13064594382 |
Front-end for capturing Action Relation Level models using dataclasses |
2025-01-31 01:29:39 |
| cocotbext-ahb |
0.4.9 |
CocotbExt AHB Bus VIP |
2025-01-25 18:58:04 |
| pyvsc-dataclasses |
0.0.1.12773179088 |
Front-end for capturing Verification Stimulus and Coverage constructs using dataclasses |
2025-01-14 17:33:41 |
| peakrdl-regblock |
0.23.0 |
Compile SystemRDL into a SystemVerilog control/status register (CSR) block |
2024-12-20 06:06:20 |