PyDigger - unearthing stuff about Python


NameVersionSummarydate
peakrdl-busdecoder 0.4.0 Generate a SystemVerilog bus decoder from SystemRDL for splitting CPU interfaces to multiple sub-address spaces 2025-10-29 06:43:45
pyhdl-if 0.0.6.18859960599 Python interface for HDL programming interfaces 2025-10-28 00:26:08
peakrdl-etana 0.1.0 Compile SystemRDL into a SystemVerilog control/status register (CSR) block 2025-10-27 23:01:34
pyucis 0.1.4.18685268604 PyUCIS provides a Python API for manipulating UCIS coverage data. 2025-10-21 13:23:02
bin2hex 2.1.0 bin2hex is an utility to convert binary file to multiple types of hexadecimal text file 2025-09-15 15:21:49
pyrilog 0.2.4 A Python-based SystemVerilog code generator using context managers 2025-09-09 18:02:31
hdl-parser 1.0.1 Easy-To-Use SystemVerilog Parser 2025-09-08 13:41:45
fltools 0.0.1.17506416626 Provides utilities for working with EDA Filelists 2025-09-05 23:09:04
oshsh 0.0.1 A package for forging HDL. 2025-08-29 08:25:29
hdl-forge 0.0.1 A package for forging HDL. 2025-08-29 08:23:02
vsc-dm 0.0.1.17196494297 Core Verification Stimulus and Coverage library 2025-08-25 01:20:40
BICSdifftest 1.0.1 Differential Testing Framework for Verilog Hardware Verification 2025-08-24 09:24:01
jtag-axi 0.1.5 JTAG to AXI bridge python I/F 2025-08-20 09:29:31
mooreio-client 2.1.9 CLI tool to automate EDA tasks for ASICs, FPGAs, and UVM IP. 2025-08-19 02:13:13
peakrdl-viz 1.0.2 Generate visualization code for MakerChip VIZ framework. 2025-08-13 18:29:39
pytcl-eda 0.3.0 PyTCL allows control EDA tools directly from Python that use TCL 2025-08-11 07:27:29
pyslang 9.0.0 Python bindings for slang, a library for compiling SystemVerilog 2025-07-31 12:18:48
hdltree 0.5.2 Pure Python HDL parser, plus symbol generator and sphinx domain 2025-07-13 23:19:51
zuspec-be-py 0.0.1.14003524440 Co-specification of hardware, software, design, and test behavior 2025-03-22 00:56:45
vsc-solvers 0.0.1.13937968163 Core Verification Stimulus and Coverage library 2025-03-19 03:09:55
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